The ongoing scaling of transistors presents an ever expanding array of new issues to be overcome as the transistor dimensions shrink. Once such issue concerns guarding against contacts shorting to the gate structures as the transistors are scaled to ever smaller dimensions. Historically, contact-to-gate shorting has been a key obstacle to aggressive transistor dimensional scaling owing to the extreme difficulty of placing diffusion contacts between closely spaced transistor gates.
FIGS. 1a-1d represent a conventional process flow for providing contacts to the diffusion of a transistor structure. As seen in FIG. 1a, a transistor structure 100 includes a pair of gates 102 disposed next to each other on a substrate 103, spacers 104 at each side of each of the gates, and a diffusion layer 106 between the pair of gates. The diffusion layer 106 may include a source region between the two gates, and drain regions on opposite sides of the gates (not designated in the figures), or vice versa. Referring next to FIG. 1b, the prior art deposits an oxide layer 108 onto the gates and diffusion layer as shown, such as, for example, by way of chemical vapor deposition. FIG. 1c in turn shows the oxide layer 108 as having been patterned to define a contact opening 110 therein. The contact opening 110 may typically be provided using well known lithography and etching techniques. Thereafter, as shown in FIG. 1d a conductive material may be provided inside the contact opening 110 to provide a contact plug 112. The contact opening 110 may for example be filled using an electroless and/or an electrolytic plating technique. The resulting transistor structure 100 shown in FIG. 1d poses a concern with respect to a possible shorting between the contact plug 112 and each of the gates 102, as suggested by example by arrows S. The above becomes even more of a concern as a function of the generational scaling of transistor geometries.
The prior art attempts to solve the above issues by either making the contact plugs smaller, tightening alignment requirements between the contact masking layer and the gate masking layer, and/or providing larger transistors. Smaller contact plugs, however, by virtue of an increased resistance of the plug, can lead to degraded transistor performance. In addition, smaller contact openings may be difficult to fill with the conductive plug material, in this way affecting process margins. Tightening alignment requirements between the contact masking layer and the gate masking layer, on the other hand, presents limitations as well, to the extent that, since alignment is a mechanical process, and since limits of tool alignment are rapidly being approached with the scaling of transistor structures, such tightening may not be a viable option for future generation transistors. Larger transistors, on the other hand, significantly impact both transistor performance and the need for a generational scaling of transistor and chip sizes.
The prior art fails to provide a cost-effective and reliable manner of reducing the possibility of contact to gate shorting in a transistor structure.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.